+
    TBiX                         R t ^ RIt^ RIHtHtHtHtHtHt ^ RI	H
t
HtHtHtHtHtHtHtHt . R
Ot ! R R]4      t ! R R]4      t ! R	 R]4      tR# )z
pygments.lexers.hdl
~~~~~~~~~~~~~~~~~~~

Lexers for hardware descriptor languages.

:copyright: Copyright 2006-2025 by the Pygments team, see AUTHORS.
:license: BSD, see LICENSE for details.
N)
RegexLexerbygroupsincludeusingthiswords)	TextCommentOperatorKeywordNameStringNumberPunctuation
WhitespaceVerilogLexerSystemVerilogLexer	VhdlLexerc                     a  ] tR t^t o RtRtRR.tR.tR.tRt	Rt
RtR	R
]P                  R3R]3R]! ]P"                  ]4      3R]P$                  3R]P&                  3R]3R]R3R]P*                  3R]P.                  3R]P.                  3R]P0                  3R]P2                  3R]P4                  3R]P6                  3R]3R]P4                  3R]3R]3R]P<                  3R]! ]]P@                  ]!4      3R ]! ]]P@                  ]!4      R!3]"! R9R"R#7      ]3]"! R:R$R"R%7      ]P                  3]"! R;R&R"R%7      ]PF                  3]"! R<R"R#7      ]PH                  3R']PJ                  3R(]3R)]3.RR*]R+3R,]P"                  3R-]3R]! ]P"                  ]4      3R.]3.RR/]P                  3R0]P&                  3R1]P$                  R+3R2]P                  3R3]P                  3R4]R+3.R!R5]P@                  R+3./t&R6 t'R7t(V t)R8# )=r   z7
For verilog source code with preprocessor directives.
verilogvz*.vztext/x-verilogz%https://en.wikipedia.org/wiki/Verilogz1.4(?:\s|//.*?\n|/[*].*?[*]/)+rootz^\s*`definemacro\s+(\\)(\n)/(\\\n)?/(\n|(.|\n)*?[^\\]\n)/(\\\n)?[*](.|\n)*?[*](\\\n)?/[{}#@]L?"string4L?'(\\.|\\[0-7]{1,3}|\\x[a-fA-F0-9]{1,2}|[^\\\'\n])'%(\d+\.\d*|\.\d+|\d+)[eE][+-]?\d+[lL]?(\d+\.\d*|\.\d+|\d+[fF])[fF]?z([0-9]+)|(\'h)[0-9a-fA-F]+z([0-9]+)|(\'b)[01]+z([0-9]+)|(\'d)[0-9]+z([0-9]+)|(\'o)[0-7]+z\'[01xz]z\d+[Ll]?[~!%^&*+=|?:<>/-][()\[\],.;\']`[a-zA-Z_]\w*^(\s*)(package)(\s+)^(\s*)(import)(\s+)import\bsuffix`)prefixr,   z\$[a-zA-Z_]\w*:(?!:)\$?[a-zA-Z_]\w*\\(\S+)"#pop/\\([\\abfnrtv"\']|x[a-fA-F0-9]{2,4}|[0-7]{1,3})	[^\\"\n]+\\[^/\n]+/[*](.|\n)*?[*]/z//.*?\n/	(?<=\\)\n\n	[\w:]+\*?c                j    ^ pRV 9   d
   VR,          pRV 9   d
   VR,          pRV 9   d
   VR,          pV# )zXVerilog code will use one of reg/wire/assign for sure, and that
is not common elsewhere.regg?wireassign )textresults   & 8/usr/lib/python3.14/site-packages/pygments/lexers/hdl.pyanalyse_textVerilogLexer.analyse_text   s?     D=cMFT>cMFtcMF    rA   N)qalwaysalways_comb	always_ffalways_latchandr@   	automaticbeginbreakbufbufif0bufif1casecasexcasezcmosconstcontinuedeassigndefaultdefparamdisabledoedgeelseendendcaseendfunctionendgenerate	endmodule
endpackageendprimitive
endspecifyendtableendtaskenumeventfinalforforceforeverforkfunctiongenerategenvarhighz0highz1ifinitialinoutinputintegerjoinlarge
localparammacromodulemediummodulenandnegedgenmosnornotnotif0notif1oroutputpacked	parameterpmosposedge	primitivepull0pull1pulldownpulluprcmosrefreleaserepeatreturnrnmosrpmosrtranrtranif0rtranif1scalaredsignedsmallspecify	specparamstrengthr    strong0strong1structtabletasktrantranif0tranif1typetypedefunsignedvarvectoredvoidwaitweak0weak1whilexnorxor)
accelerateautoexpand_vectornets
celldefinedefault_nettyper_   elsifendcelldefineendif
endprotectendprotectedexpand_vectornetsifdefifndefr   noacceleratenoexpand_vectornetsnoremove_gatenamesnoremove_netnamesnounconnected_driveprotect	protectedremove_gatenamesremove_netnamesresetall	timescaleunconnected_driveundef)4bits
bitstorealbitstoshortrealcountdriversdisplayfclosefdisplayfinishfloorfmonitorfopenfstrobefwrite
getpatternhistoryincsavery   itorkeylistlogmonitor
monitoroff	monitoronnokeynologprinttimescalerandomreadmembreadmemhrealtime
realtobitsresetreset_countreset_valuerestartrtoisavescalescopeshortrealtobits
showscopesshowvariablesshowvars	sreadmemb	sreadmemhstimestopstrobetime
timeformatwrite)byteshortintintlongintrz   r   bitlogicr>   supply0supply1tritriandtriortri0tri1trireguwirer?   wandworshortrealrealr   )*__name__
__module____qualname____firstlineno____doc__namealiases	filenames	mimetypesurlversion_added_wsr	   Preprocr   r   r   EscapeSingle	Multiliner   Charr   FloatHexBinIntegerOctr
   r   Constantr   	Namespacer   r   BuiltinTypeLabeltokensrE   __static_attributes____classdictcell__)__classdict__s   @rD   r   r      s     D#GI!"I
1CM )C 	W__g6Z (6==*=>-w~~>.0A0AB$VX&DfkkR5v||D-v||<*FJJ7#VZZ0$fnn5$fjj1&!&..)!8,{+t}}-$hz7;L;Ld&ST#Xj':K:KT%R  :" CH#I$ %(   "&e5 __  W U	, \\
  1 :?	@
 \\ #DJJ/&WL
Z 	66"?O6"(6==*=>FO
 	) '"3"3407??#7??+J'
 	4>>62
{`FD rG   c                       ] tR t^tRtRtRR.tRR.tR.tRt	Rt
R	tR
. R]! ]]P                  4      R3NR]! ]]P"                  ]4      3NR]! ]]P"                  ]4      R3NR]3NR]! ]P&                  ]4      3NR]P(                  3NR]P*                  3NR]3NR]R3NR]P.                  3NR]P2                  3NR]P2                  3NR]P4                  3NR]P6                  3NR]P8                  3NR]P:                  3NR]3NR]P8                  3NR ]3N]! R9R!R"7      ]P@                  3NR#]3NR$]!PD                  3N]! R:R!R"7      ]3NR%]! ]PF                  ]]!PH                  4      3NR&]! ]PF                  ]]!PH                  4      3NR']! ]PF                  ]]]]!PH                  4      3N]! R;R!R"7      ]PJ                  3N]! R<R!R"7      ]P                  3N]! R=R!R"7      ]!PL                  3NR(]!PN                  3NR)]!3NR*]!3NRR+]R,3R-]P&                  3R.]3R]! ]P&                  ]4      3R/]3.RR0]P                  3R1]P*                  3R2]P(                  R,3R3]P                  3R4]P                  3R5]R,3.RR6]!P"                  R,3./t(R7t)R8# )>r   z]
Extends verilog lexer to recognise all SystemVerilog keywords from IEEE
1800-2009 standard.
systemverilogsvz*.svz*.svhztext/x-systemverilogz+https://en.wikipedia.org/wiki/SystemVerilog1.5r   r   z^(\s*)(`define)r   r'   r(   r)   r   r   r   r   r   r   r    r!   r"   r#   z4([1-9][_0-9]*)?\s*\'[sS]?[bB]\s*[xXzZ?01][_xXzZ?01]*z6([1-9][_0-9]*)?\s*\'[sS]?[oO]\s*[xXzZ?0-7][_xXzZ?0-7]*z6([1-9][_0-9]*)?\s*\'[sS]?[dD]\s*[xXzZ?0-9][_xXzZ?0-9]*zB([1-9][_0-9]*)?\s*\'[sS]?[hH]\s*[xXzZ?0-9a-fA-F][_xXzZ?0-9a-fA-F]*z
\'[01xXzZ]z[0-9][_0-9]*r$   r*   r+   z[()\[\],.;\'$]r&   z(class)(\s+)([a-zA-Z_]\w*)z(extends)(\s+)([a-zA-Z_]\w*)z,(endclass\b)(?:(\s*)(:)(\s*)([a-zA-Z_]\w*))?r/   r0   r1   r2   r3   r4   r5   r6   r7   r8   z//.*?$r9   r:   r;   r<   rA   N)insidedist)	accept_onaliasrH   rI   rJ   rK   rL   assertr@   assumerM   beforerN   bindbinsbinsofrO   rP   rQ   rR   rS   rT   rU   cellcheckerclockingrV   config
constraintcontextrX   cover
covergroup
coverpointcrossrY   rZ   r[   designr\   r]   r^   r_   r`   ra   
endcheckerendclocking	endconfigrb   rc   endgroupendinterfacerd   re   rf   
endprogramendpropertyendsequencerg   rh   ri   rj   
eventuallyexpectexportexternrl   first_matchrm   rn   foreachro   rp   forkjoinrq   rr   rs   globalrt   ru   rv   iffifnoneignore_binsillegal_binsimplies
implementsr)   incdirr   rw   rx   ry   instanceinterconnect	interface	intersectr{   join_any	join_noner|   letliblistlibrarylocalr}   r~   matchesr   modportr   r   r   nettypenewnexttimer   r   noshowcancelledr   r   r   nullr   r   packager   r   r   r   r   priorityprogrampropertyr   r   r   r   r   pulsestyle_ondetectpulsestyle_oneventpurerandrandcrandcaserandsequencer   r   	reject_onr   r   restrictr   r   r   r   r   r   s_alwayss_eventually
s_nexttimes_untils_until_withr   sequenceshowcancelledr   softsolver   r   staticstrongr   r   r   supersync_accept_onsync_reject_onr   taggedr   r   
throughouttimeprecisiontimeunitr   r   r   r   unionuniqueunique0until
until_withuntypeduser   virtualr   
wait_orderweakr   r   r   wildcardwithwithinr   r   )!r  r  chandlerW   rk   r  rz   r  r  r  r   r>   r  	shortrealr   r    r   r   r   r   r   r	  r
  r  r  r  r  r  r  r  r  r?   wor)z	`__FILE__z	`__LINE__z`begin_keywordsz`celldefinez`default_nettypez`definez`elsez`elsifz`end_keywordsz`endcelldefinez`endifz`ifdefz`ifndefz`includez`linez`nounconnected_drivez`pragmaz	`resetallz
`timescalez`unconnected_drivez`undefz`undefineall)z$exitz$finishz$stopz	$realtimez$stimez$timez$printtimescalez$timeformatz$bitstorealz$bitstoshortrealz$castz$itorz$realtobitsz$rtoiz$shortrealtobitsz$signedz	$unsignedz$bitsz$isunboundedz	$typenamez$dimensionsz$highz
$incrementz$leftz$lowz$rightz$sizez$unpacked_dimensionsz$acosz$acoshz$asinz$asinhz$atanz$atan2z$atanhz$ceilz$clog2z$cosz$coshz$expz$floorz$hypotz$lnz$log10z$powz$sinz$sinhz$sqrtz$tanz$tanhz
$countbitsz
$countonesz
$isunknownz$onehotz$onehot0z$infoz$errorz$fatalz$warningz$assertcontrolz$assertfailoffz$assertfailonz$assertkillz$assertnonvacuousonz
$assertoffz	$assertonz$assertpassoffz$assertpassonz$assertvacuousoffz$changedz$changed_gclkz$changing_gclkz$falling_gclkz$fellz
$fell_gclkz$future_gclkz$pastz
$past_gclkz$rising_gclkz$rosez
$rose_gclkz$sampledz$stablez$stable_gclkz$steady_gclkz$coverage_controlz$coverage_getz$coverage_get_maxz$coverage_mergez$coverage_savez$get_coveragez$load_coverage_dbz$set_coverage_db_namez$dist_chi_squarez$dist_erlangz$dist_exponentialz$dist_normalz$dist_poissonz$dist_tz$dist_uniformz$randomz$q_addz$q_examz$q_fullz$q_initializez	$q_removez$async$and$arrayz$async$and$planez$async$nand$arrayz$async$nand$planez$async$nor$arrayz$async$nor$planez$async$or$arrayz$async$or$planez$sync$and$arrayz$sync$and$planez$sync$nand$arrayz$sync$nand$planez$sync$nor$arrayz$sync$nor$planez$sync$or$arrayz$sync$or$planez$systemz$displayz	$displaybz	$displayhz	$displayoz$monitorz	$monitorbz	$monitorhz	$monitoroz$monitoroffz
$monitoronz$strobez$strobebz$strobehz$strobeoz$writez$writebz$writehz$writeoz$fclosez	$fdisplayz
$fdisplaybz
$fdisplayhz
$fdisplayoz$feofz$ferrorz$fflushz$fgetcz$fgetsz	$fmonitorz
$fmonitorbz
$fmonitorhz
$fmonitoroz$fopenz$freadz$fscanfz$fseekz$fstrobez	$fstrobebz	$fstrobehz	$fstrobeoz$ftellz$fwritez$fwritebz$fwritehz$fwriteoz$rewindz$sformatz	$sformatfz$sscanfz$swritez$swritebz$swritehz$swriteoz$ungetcz	$readmembz	$readmemhz
$writemembz
$writememhz$test$plusargsz$value$plusargsz$dumpallz	$dumpfilez
$dumpflushz
$dumplimitz$dumpoffz$dumponz
$dumpportsz$dumpportsallz$dumpportsflushz$dumpportslimitz$dumpportsoffz$dumpportsonz	$dumpvars)*r  r  r  r  r  r  r  r  r  r  r  r   r   r   r	   r!  r   r,  r   r"  r#  r$  r   r%  r   r&  r(  r*  r)  r'  r
   r   Wordr   r+  DeclarationClassr.  r-  r/  r0  r1  rA   rG   rD   r   r      sO    D%G!I'(I
7CM )C 	 }
*goo!FP}
$hz7;L;Lj&YZ}
 $Xj':K:KZ%XZbc}

 Z }
 (6==*=>}
 .w~~>}
 /0A0AB}
 $}
 VX&}
 EfkkR}
 6v||D}
 .v||<}
  EZZ!}
$ GZZ%}
( G^^)}
, SZZ-}
2 F#3}
4 fnn-5}
8 "8,9}
: %e4hmmD;}
> ,?}
@ t}}-A}
D  (R S)T U*E}
\ +g)):tzzBD]}
` -g)):tzzBDa}
d =g)):{JPTPZPZ[]e}
j  @ 	 \\
k}
B  N  __C}
T  MZ  [M!\ \\]NU}
t #DJJ/u}
v  &w}
x y}
| 	66"?O6"(6==*=>FO
 	) '"3"34/7??#7??+J'
 	4>>62
]QFrG   c                   4   ] tR tRtRtRtR.tRR.tR.tRt	Rt
]P                  ]P                  ,          tR	R
]3R]! ]P$                  ]4      3R]P(                  3R]P*                  3R]P,                  3R]3R]P2                  3R]3R]3R]! ]]]P8                  4      3R]! ]]]4      3R]! ]]]P8                  ]4      3R]! ]]]P8                  4      3R]! ]P8                  ]P8                  4      3]! R-RR7      ]P8                  3R]! ]]]P<                  4      3R]! ]]]P<                  ]]]]P<                  ]]4	      3R]! ]P<                  ]]]4      3R]! ]! ] 4      ]4      R3]!! R4      ]!! R 4      ]!! R!4      R"]3.R]!! R 4      R"]P<                  3R
]3R#]R$3.R]! R.RR7      ]PD                  3.R ]! R/RR7      ]3.R!R%]#PH                  3R&]#PH                  3R']#PJ                  3R(]#PL                  3R)]#PN                  3R*]#PP                  3./t)R+t*R,# )0r   iu  z
For VHDL source code.
vhdlz*.vhdlz*.vhdztext/x-vhdlz"https://en.wikipedia.org/wiki/VHDLr7  r   r   r   z--.*?$r   z'(U|X|0|1|Z|W|L|H|-)'r$   z
'[a-z_]\w*r%   z"[^\n\\"]*"z(library)(\s+)([a-z_]\w*)z(use)(\s+)(entity)z(use)(\s+)([a-z_][\w.]*\.)(all)z(use)(\s+)([a-z_][\w.]*)z(std|ieee)(\.[a-z_]\w*)r*   r+   z"(entity|component)(\s+)([a-z_]\w*)zN(architecture|configuration)(\s+)([a-z_]\w*)(\s+)(of)(\s+)([a-z_]\w*)(\s+)(is)z ([a-z_]\w*)(:)(\s+)(process|for)z
(end)(\s+)endblocktypeskeywordsnumbersz	[a-z_]\w*;r3   z\d{1,2}#[0-9a-f_]+#?z\d+z(\d+\.\d*|\.\d+|\d+)E[+-]?\d+zX"[0-9a-f_]+"z
O"[0-7_]+"z	B"[01_]+"rA   N)stdieeework)booleanr  	characterseverity_levelrz   r   delay_lengthnaturalpositiver    
bit_vectorfile_open_kindfile_open_status
std_ulogicstd_ulogic_vector	std_logicstd_logic_vectorr   r   )_absaccessafterr;  allrL   architecturearrayr<  	attributerN   blockbodybufferbusrS   	componentconfigurationconstant
disconnectdowntor_   r   r`   entityexitfilerm   rq   rr   genericgroupguardedrv   impureininertialrx   islabelrl  linkageliteralloopmapmodr   rq  nextr   r   rt  ofonopenr   othersoutru  port	postponed	procedureprocessr{  rangerecordregisterrejectremr   rolrorselectseveritysignalsharedslasllsrasrlsubtypethento	transportr   unitsr  r  variabler   whenr   r  r   r   )+r  r  r  r  r  r  r  r  r  r  r  re	MULTILINE
IGNORECASEflagsr   r   r   r"  r	   r#  r$  r%  r
   r   	Attributer   r   r,  r   r  r   r   r   r.  r   r)  r&  r'  r*  r(  r0  r1  rA   rG   rD   r   r   u  s    DhG7#II
.CMLL2==(E 	Z (6==*=>'.0A0AB%v{{3!8,DNN+{+V$)gz4>>:<"HWj'$JK/gz4>>7CE(gz4>>:<'dnndnn57*59^^2gz4::68.gz4::z7Jjj*g78 1djj(J@BHU4[*=zJGJI4 I%
L 	J4::&Z ;'	
 	 G PU	V
 \\
 	 0  9>!?" #
( 	$fnn5V^^$-v||<vzz*FJJ'6::&
SQFrG   )r   r   r   )r  r  pygments.lexerr   r   r   r   r   r   pygments.tokenr   r	   r
   r   r   r   r   r   r   __all__r   r   r   rA   rG   rD   <module>r     sW    
 L L$ $ $ >{: {|` `F]
 ]rG   